Engineer – JTAG & SCANDUMP

April 14, 2023
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Job Description

Key Responsibilities include:

  • Implement BSDL and JTAG setup at the chip level.
  • Setup Pattern generation flow for BSDL/JTAG and timely delivery of vectors as per PTE requirement
  • 1-2 years of experience.
  • Understanding of JTAG IEEE-1149.1 standard.
  • Experience in JTAG verification.
  • Good understanding of Boundary scan architecture.
  • Proven experience in successfully delivering projects on-time, timely communication on projects progress, and close collaboration with partners
  • RTL, GLS, PA-RTL/GLS debug skills is must.
  • Scripting language (perl preferred).
  • Knowledge on IJTAG P1687 standard would be an add-on advantage.
  • Should be a good problem solver.
  • Important skill sets required: System Verilog, Basics of UVM and preferably System Verilog assertions

Minimum Qualifications:• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Preferred Qualifications:

•    Master’s degree in Computer Science, Engineering, Information Systems, or related field.
•    1+ year of experience with circuit design (e.g., digital, analog, RF).

•    1+ year of experience utilizing schematic capture and circuit simulation software.

•    1+ year of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.

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