Job ID : 1577510
Batch: 2018 & Earlier
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The Microsoft Silicon Engineering Team is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas such as Continuous Integration, SCM, RTL Design, Design Verification, Validation, DFT, Emulation and IP integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft.
In this role, you will own re-usable SystemVerilog building blocks that are consumed as libraries by all internal IP and SoC silicon development efforts. Your day-to-day activities will include:
- Active development of incoming enhancement requests from our silicon design teams.
- Continual improvement of overall quality and performance of the existing building blocks
- Library releases to design teams following rigorous checklist criteria per intercept milestone.
- Active support for incoming bugs, issues, and questions related to these libraries.
- Work closely with silicon teams to collect new requirements needed for upcoming products.
- Be an expert in the FE domain and act in partnership with the execution teams.
- Provide leadership to the design community for the FE CAD domain.
- Do you have a BS in Electrical Engineering, Computer Engineering, or equivalent work experience?
- Do you have 5+ years of experience in digital design or CAD tool development?
- Are you well-rounded and familiar with most Front-End Tools, Flows and Methodologies?
- Do you have experience writing scripts/software with industry standard languages such as Python, TCL, Perl, C/C++ or SystemC?
- Do you have experience with design and verification of reusable design components using SystemVerilog?
- Are you well rounded in the following areas: Logic design, Design Verification, Validation, Static Tool Analysis, Synthesis, Design Integration, Design and Verification IP Libraries, Verilog Generators, and Low Power design.
- MS in Electrical Engineering, Computer Engineering, or equivalent work experience.
- 10+ years of relevant experience in FE CAD
- Experience with foundry IP and understanding how this collateral is consumed in silicon design flows.
- Experience with CI/CD, and integration into SCM systems.
- Expertise in Computer Architecture, as well as CPU/SoC design principles.
- In-depth knowledge of Front-End workflows, methodologies, and best practices.
- In-depth knowledge of verification workflows, methodologies, and best practices.
- Experience with the debug and bring-up of SOC and sub-system level designs.
- Experience defining, developing, and using verification environments in industry standard languages like UVM.
- Knowledge or experience with Formal verification and/or Emulation.